Suresh Govindachar's Work Experience


My work interest is that of an engineer involved in all aspects of embedded/real-time Software/HDL (on uni-/multi- processors and/or FPGAs).

In general, my work experience has been in all aspects of high-speed, real-time embedded applications: from algorithm development -- to architecting the system -- to implementation of the device driver, the core application, and the host code -- to board bring-up. The coding experience has been in C, assembly and HDL; and for uni-/multi- processors and/or FPGAs. Most of this work was within the NASA/defense/telecommunications industry.

The applications I have worked on include

These applications were either on FPGAs (e.g., 10 Altera 10K100) or C-processors (e.g., 32 processor VME system from Mercury Computer Systems and the CGN16100, a networking chip with 16 processors).

Recent Work (10G Multilayer Network Packet Processing)

My past employer was Cognigine Corporation. Cognigine produced the CGN16100, a networking chip with 16 processors targeting the 10 Gbits/s, multi-layer network packet processing market. Last year, the assets of Cognigine were purchased by a competitor (based in China) of Cisco.

At Cognigine, I researched IP-RFCs and Fabric and Framer chipsets and developed applications that demonstrated the capabilities of the CGN16100.

I studied the CPU and the Interconnect network within the 16 processor CGN16100, including bus transfer cycles, dma engine and latencies. Thereby, I became adept at exploiting the features of the CGN16100 and at developing and validating high performance, real-time code on it.

I developed switching, routing and services applications for the CGN16100: layer2, MPLS, IPv4, 1812, MDRR, RED, Metering and Marking, TCP/IP termination and Offload Engine (TOE); with interfaces to Mindspeed's 27300 fabric chipset and to SPI-4 framer I/O protocol.

To validate the correctness of the above applications and to characterize their performance, I also developed traffic generators and test-benches. The tests for the TCP/IP Offload Engine (TOE) included demonstration of the compatibility of the developed TCP/IP code with the standard TCP/IP kernel found on a Linux workstation.

I also defined and developed tools/scripts to assist in the development of the above applications.

I identified a need for facilitating the development of CGN16100 applications in assembly code including need for non-conflicting integration of assembly code from multiple developers. And I solved this problem by defining a language, called Real. Not only did Real make it easy to write assembly instructions it also did memory management. The memory management allowed the writing of code without concern for the physical memory addresses, and it allowed code from different developers to be combined without concern for memory corruption. I also wrote the real compiler that converted Real code to assembly code. This compiler was in perl.

Biggest Project

The customer for the biggest project I worked on wanted a ''High Speed Digital Controller (HSDC)'': HSDC was a combined hardware and software product. The hardware was 18 16-bit sensors (A/D) and 18 16-bit actuators (D/A) with the ability to trigger all 36 ADCs simultaneously at 100 KSamples/s with no pipeline delay (so the ADCs couldn't be sigma-delta ADCs). The software could either be pumping data to the D/A while collecting data from the A/D or it could be getting data from the A/D, performing digital control algorithms on this data and sending the results to the D/A while also collecting the raw A/D data. There had to be a graphical, iconic, point-and-click user interface for the customer to decide what the software should do and, when it was performing digital control, which particular feedback control law was being implemented. The user was to be able to implement any mathematically expressible control law with the GUI. Such was what the customer wanted.

The stringent, state-of-the-art requirements included:

They wanted the product in one year. They invited competitive proposals for the solution with proof of concept demonstrations. They visited about 10 firms in the US -- including major defence contractors -- and evaluated the proposals. The small firm I was working at won the bid (Firm Fixed Price Contract).

In this project I:

The budget for this one year project was about 640K (Firm Fixed Price Contract). The project was successfully finished on time and within budget.

Video/Image Processing

I have worked on several projects involving video/image processing. The specific tasks I did include:

The maximum video data rate I have worked with was from 6 gen-locked, progressive 640x480 cameras, 2 Bytes/pixel and running at 30 Hz -- which corresponds to over 110 MB/s.

An Interesting, Practical Problem Involving Projective Geometry

An interesting project which involved projective geometry was architecting a multi-camera passive, dynamic measurement system and developing the associated algorithms for the measurement in a lab setting of a levitating (14'' long x 2'' dia) cylinder with 6 degrees of freedom. The measurement system provided over 100 measurements per second with roll, pitch, yaw accuracy better than 1 milliradians (1 sigma) and x, y, z displacement accuracy better than 3 mils (0.003''; 1 sigma).

Smallest Firm I have Worked For

I worked at a small firm for about seven years. During that time, the number of employees varied roughly from 5 to 20.


My formal education has been:

     PhD   Cornell University,  Ithaca, New York
           Department of Mathematics, August 1992 (Published Research)
     MS    Cornell University,  Ithaca, New York
           Department of Mathematics, May 1989 (GPA: 4.1/4)
     MS    Cornell University,  Ithaca, New York
           Theoretical and Applied Mechanics, May 1985 (GPA: 4.1/4)
     BTech Indian Institute of Technology,  Bombay, India
           Mechanical Engineering, May 1983 (GPA: 3.9/4)
 Suresh Govindachar's Work Experience